Creating Assertion-Based IP (Integrated Circuits and Systems)

Foster, Harry D.

ISBN 10: 0387366415 / ISBN 13: 9780387366418

Edité par Springer, 2007

A propos de cet article

Most items will be dispatched the same or the next working day. An apparently unread copy in perfect condition. Dust cover is intact with no nicks or tears. Spine has no signs of creasing. Pages are clean and not marred by notes or folds of any kind.

N° de réf. du vendeur wbs5143181861

Détails bibliographiques

• Titre: Creating Assertion-Based IP (Integrated Circuits and Systems)
• Éditeur: Springer
• Date de parution: 2007
• Langue: anglais
• ISBN à 10 chiffres: 0387366415
• ISBN à 13 chiffres: 9780387366418
• Reliure: Couverture rigide
• État de l'article: Like New

A propos de ce titre

Synopsis

A project's functional verification testplan is the specification for the verification process. Developing this testplan usually involves the entire engineering team (architects, designers, and verification engineers). This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. This is the first book published on this subject. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions. Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP.