Digital Design of SDRAM on Verilog

Abhishek Kumar

ISBN 10: 6204727672 / ISBN 13: 9786204727677

Edité par LAP LAMBERT Academic Publishing, 2021

A propos de cet article

nach der Bestellung gedruckt Neuware - Printed after ordering - To design an 8 MB x 16 x 4-BAnk synchronous random access dynamic memory (SDRAM) (512 MB) using Verilog hardware description language, which can be used in any memory-based application. Today, computers, as well as other electronic systems that require large amounts of memory, use DRAMs for core memory. Due to the unique transistor cell structure of the DRAM, extremely dense memory networks can be constructed in a single device occupying a relatively small footprint. The conventional DRAM is controlled in an asynchronous manner, requiring the system designer to manually insert the standby states to meet the device specifications. Synchronization timing is dependent on DRAM speed and is independent of system bus speed. It is these limitations of synchronization that have led to the development of the SDRAM. The SDRAM is largely a fast DRAM with a high-speed synchronous interface. Input/output and controller signals are synchronized with an external clock, making new options available to the designer. Simplified interface circuits and high bandwidth data throughput can be obtained using SDRAM over conventional DRAM.

N° de réf. du vendeur 9786204727677

Détails bibliographiques

• Titre: Digital Design of SDRAM on Verilog
• Éditeur: LAP LAMBERT Academic Publishing
• Date de parution: 2021
• Langue: anglais
• ISBN à 10 chiffres: 6204727672
• ISBN à 13 chiffres: 9786204727677
• Reliure: Taschenbuch
• État de l'article: Neu

A propos de ce titre

Synopsis

To design an 8 MB x 16 x 4-BAnk synchronous random access dynamic memory (SDRAM) (512 MB) using Verilog hardware description language, which can be used in any memory-based application. Today, computers, as well as other electronic systems that require large amounts of memory, use DRAMs for core memory. Due to the unique transistor cell structure of the DRAM, extremely dense memory networks can be constructed in a single device occupying a relatively small footprint. The conventional DRAM is controlled in an asynchronous manner, requiring the system designer to manually insert the standby states to meet the device specifications. Synchronization timing is dependent on DRAM speed and is independent of system bus speed. It is these limitations of synchronization that have led to the development of the SDRAM. The SDRAM is largely a fast DRAM with a high-speed synchronous interface. Input/output and controller signals are synchronized with an external clock, making new options available to the designer. Simplified interface circuits and high bandwidth data throughput can be obtained using SDRAM over conventional DRAM.