Digital Logic Design Using Verilog: Coding and RTL Synthesis

Taraate, Vaibbhav

ISBN 10: 9811632014 / ISBN 13: 9789811632013

Edité par Springer, 2022

A propos de cet article

N° de réf. du vendeur ABLIING23Apr0412070092177

Détails bibliographiques

• Titre: Digital Logic Design Using Verilog: Coding and RTL Synthesis
• Éditeur: Springer
• Date de parution: 2022
• Langue: anglais
• ISBN à 10 chiffres: 9811632014
• ISBN à 13 chiffres: 9789811632013
• Reliure: Couverture souple
• Édition: 2ème Édition
• État de l'article: New

A propos de ce titre

Synopsis

Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.

À propos de l?auteur

Vaibbhav Taraate is an entrepreneur and mentor at "1 Rupee S T". He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.