Equivalence Checking of Digital Circuits

Molitor, Paul (Martin-Luther-University Halle-Wittenberg, Germany); Mohnke, Janett (DResearch Digital Media Systems GmbH, Germany)

ISBN 10: 1441954236 / ISBN 13: 9781441954237

Edité par Springer-Verlag New York Inc., 2010

A propos de cet article

Num Pages: 263 pages, biography. BIC Classification: TJF. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 14. Weight in Grams: 433. . 2010. Softcover reprint of the original 1st ed. 2004. Paperback. . . . .

N° de réf. du vendeur V9781441954237

Détails bibliographiques

• Titre: Equivalence Checking of Digital Circuits
• Éditeur: Springer-Verlag New York Inc.
• Date de parution: 2010
• Langue: anglais
• ISBN à 10 chiffres: 1441954236
• ISBN à 13 chiffres: 9781441954237
• Reliure: Couverture souple
• État de l'article: New

A propos de ce titre

Synopsis

Hardware veri?cation is the process of checking whether a design conforms to its speci?cations of functionality and timing. In today’s design processes it becomes more and more important. Very large scale integrated (VLSI) circuits and the resulting digital systems have conquered a place in almost all areas of our life, even in security sensitive applications. Complex digital systems control airplanes, have been used in banks and on intensive-care units. Hence, the demand for error-free designs is more important than ever. In addition, economic reasons underline this demand as well. The design and production process of present day VLSI-circuits is highly time- and cost-intensive. Mo- over, it is nearly impossible to repair integrated circuits. Thus, it is desirable to detect design errors early in the design process and not just after producing the prototype chip. All these facts are re?ected by developing and prod- tion statistics of present day companies. For example, In?neon Technologies [118] assumed that about 60% to 80% of the overall design time was spent for veri?cation in 2000. Other sources cite the 3-to-1 head count ratio between veri?cation engineers and logic designers. This shows that verifying logical correctness of the design of hardware systems is a major gate to the problem of time-to-market (cf. [113]). With the chip complexity constantly increasing, the dif?culty as well as the - portance of functional veri?cation of new product designs has been increased. It is not only more important to get error-free designs.