Full-Chip Nanometer Routing Techniques

Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-jie

ISBN 10: 1402061943 / ISBN 13: 9781402061943

Edité par Springer, 2007

A propos de cet article

Unread book in perfect condition.

N° de réf. du vendeur 5184010

Détails bibliographiques

• Titre: Full-Chip Nanometer Routing Techniques
• Éditeur: Springer
• Date de parution: 2007
• Langue: anglais
• ISBN à 10 chiffres: 1402061943
• ISBN à 13 chiffres: 9781402061943
• Reliure: Couverture rigide
• État de l'article: As New

A propos de ce titre

Synopsis

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.