Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

Takayasu Sakurai/ Akira Matsuzawa/ Takakuni Douseki

ISBN 10: 1441939776 / ISBN 13: 9781441939777

Edité par Springer, 2006

A propos de cet article

426 pages. 9.40x6.20x1.20 inches. In Stock.

N° de réf. du vendeur x-1441939776

Détails bibliographiques

• Titre: Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
• Éditeur: Springer
• Date de parution: 2006
• Langue: anglais
• ISBN à 10 chiffres: 1441939776
• ISBN à 13 chiffres: 9781441939777
• Reliure: Paperback
• État de l'article: Brand New

A propos de ce titre

Synopsis

The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.

À propos de l?auteur

Takayasu Sakurai received the Ph.D degree in Electronic Engineering from University of Tokyo, Japan, in 1981 and he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, BiCMOS ASIC's, RISC's, and multimedia VLSI's. He worked on simple yet accurate interconnect delay, capacitance and MOS models widely used as alpha power-law MOS model. He proposed to sense-amplifying flip-flops, variable threshold voltage CMOS scheme, dual voltage converter scheme, hot carrier resilient circuits and other numerous digital and memory circuits, which are adopted in current high-performance, low-power VLSI's. He was a visiting researcher at University of California, Berkeley from 1988 to 1990. In 1996, he moved to University of Tokyo and is consulting to US startup companies. He has published about 250 technical publications including more than 30 invited papers and 6 books and filed about 100 patents. He is a recipient of four product awards and two design contest awards. He served as a conference chair for the Symposium on VLSI Circuits, and a technical program committee member for ISSCC, CICC, DAC, ICCAD, FPGA workshop, ISLPED, ASPDAC, TAU, and other international conferences. He is a keynote speaker for the 2003 ISSCC. He is an IEEE Fellow, an elected Administration Committee member for the IEEE Solid-State Circuits Society and an IEEE CAS distinguished lecturer.