A HDL & Verilog Code | Simulated Output

Manu Sudhan (u. a.)

ISBN 10: 3848423243 / ISBN 13: 9783848423248

Edité par LAP LAMBERT Academic Publishing, 2012

A HDL & Verilog Code | Simulated Output | Manu Sudhan (u. a.) | Taschenbuch | 132 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783848423248 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. N° de réf. du vendeur 106572380

Synopsis :

In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between hierarchies of blocks are properly classified as netlist languages used on electric computer-aided design (CAD).

À propos de l?auteur: B S Manusudhan/ECE/ATME College of Engineering,best academic achievement awardee.Core inventor of CBICT .Published many research papers in national & international level.Working on VLSI domain for designing "ATME-P2011" Processor.

Détails bibliographiques

Titre : A HDL & Verilog Code | Simulated Output
Éditeur : LAP LAMBERT Academic Publishing
Date d'édition : 2012
Reliure : Taschenbuch
Etat : Neu