Hardware Component Modeling (Current Issues in Electronic Modeling, 5)

ISBN 10: 0792396863 / ISBN 13: 9780792396864

Edité par Springer, 1996

A propos de cet article

NO HIGHLIGHTING: ALMOST NEW: Hardware Component Modeling 1996 HARDCOVER Hardware Component Modeling (Current Issues in Electronic Modeling, 5) 1996th Edition by Jean-Michel Bergé (Editor), Oz Levia (Editor), Jacques Rouillard (Editor) OUR REFERENCE: 132D14-HC-0792396863-2-LB-BLU-1996 DESCRIPTION The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL­ based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2. roduct details Publisher ‏ : ‎ Springer; 1996th edition (March 31, 1996) Language ‏ : ‎ English Hardcover ‏ : ‎ 152 pages ISBN-10 ‏ : ‎ 0792396863 ISBN-13 ‏ : ‎ 978-0792396864.

N° de réf. du vendeur 132D13-HC-0792396863-2-LB-BLU-1996

Détails bibliographiques

• Titre: Hardware Component Modeling (Current Issues in Electronic Modeling, 5)
• Éditeur: Springer
• Date de parution: 1996
• Langue: anglais
• ISBN à 10 chiffres: 0792396863
• ISBN à 13 chiffres: 9780792396864
• Reliure: Hardcover
• État de l'article: Very Good

A propos de ce titre

Synopsis

The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL- based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2.