High-performance Computing on the Intel Xeon Phi : How to Fully Exploit Mic Architectures

Wang, Endong; Zhang, Qing; Shen, Bo; Zhang, Guangyong; Lu, Xiaowei

ISBN 10: 3319358790 / ISBN 13: 9783319358796

Edité par Springer, 2016

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N° de réf. du vendeur 27232381-n

Détails bibliographiques

Titre : High-performance Computing on the Intel Xeon...

Éditeur : Springer

Date d'édition : 2016

Reliure : Couverture souple

Etat : New

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Synopsis :

The aim of this book is to explain to high-performance computing (HPC) developers how to utilize the Intel® Xeon Phi™ series products efficiently. To that end, it introduces some computing grammar, programming technology and optimization methods for using many-integrated-core (MIC) platforms and also offers tips and tricks for actual use, based on the authors’ first-hand optimization experience.

The material is organized in three sections. The first section, “Basics of MIC”, introduces the fundamentals of MIC architecture and programming, including the specific Intel MIC programming environment. Next, the section on “Performance Optimization” explains general MIC optimization techniques, which are then illustrated step-by-step using the classical parallel programming example of matrix multiplication. Finally, “Project development” presents a set of practical and experience-driven methods for using parallel computing in application projects, including how to determine if a serial or parallel CPU program is suitable for MIC and how to transplant a program onto MIC.

This book appeals to two main audiences: First, software developers for HPC applications – it will enable them to fully exploit the MIC architecture and thus achieve the extreme performance usually required in biological genetics, medical imaging, aerospace, meteorology and other areas of HPC. Second, students and researchers engaged in parallel and high-performance computing – it will guide them on how to push the limits of system performance for HPC applications.

À propos de l?auteur:

Endong Wang is the Director of the State Key Laboratory of High-Efficiency Server and Storage Technology at the Inspur-Intel China Parallel Computing Joint Lab and Senior Vice President of the Inspur Group Co., Ltd. Qing Zhang is the lead engineer of the Inspur-Intel China Parallel Computing Joint Lab and with his team he was among the first to work with the development environment of the Intel(R) Xeon processor and Intel(R) Xeon Phi(TM) coprocessor. Together they have several years of experience in HPC programming.