Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

Heinrich Meyr Rainer Leupers Tim Kogel

ISBN 10: 1402048254 / ISBN 13: 9781402048258

Edité par Springer, 2006

A propos de cet article

pp. 216.

N° de réf. du vendeur 26296852

Détails bibliographiques

• Titre: Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
• Éditeur: Springer
• Date de parution: 2006
• Langue: anglais
• ISBN à 10 chiffres: 1402048254
• ISBN à 13 chiffres: 9781402048258
• Reliure: Couverture rigide
• État de l'article: New

A propos de ce titre

Synopsis

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore's law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.