Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications (The Springer International Series in Engineering and Computer Science, 139)

McGeer, Patrick C., Brayton, Robert K.

ISBN 10: 1461367689 / ISBN 13: 9781461367680

Edité par Springer, 2012

A propos de cet article

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N° de réf. du vendeur ERICA80014613676896

Détails bibliographiques

• Titre: Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications (The Springer International Series in Engineering and Computer Science, 139)
• Éditeur: Springer
• Date de parution: 2012
• Langue: anglais
• ISBN à 10 chiffres: 1461367689
• ISBN à 13 chiffres: 9781461367680
• Reliure: Paperback
• État de l'article: Like New
• Type de livre: book

A propos de ce titre

Synopsis

This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under- estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu- racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo- ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.