Low Power and High Speed Parallel Multipliers for DSP Applications : Performance Evaluation of Low Power and High Speed Bypassing and Booth Multipliers for Digital Signal Processing

Nirlakalla Ravi

ISBN 10: 3659953423 / ISBN 13: 9783659953422

Edité par LAP LAMBERT Academic Publishing, 2016

A propos de cet article

nach der Bestellung gedruckt Neuware - Printed after ordering - The remarkable increase in transistor densities in modern VLSI systems has direct to a surge in power and energy dissipation to levels not seen before. This tendency will continue to produce as more transistors are packed into the same area. Therefore, power and energy-aware design flows are becoming trendy in both ends of the design space, high-performance and portable applications. In this study, the power and energy reduction techniques at the architecture, circuit, and device levels are presented. With the intention of diminishing power, we proposed a novel method for Conventional Array Multiplier. In the proposed design, final adder RCA is removed and the generated carry bits from the partial products are fed to the input of a full adder cell whose one of the input is zero. We applied final adder RCA removal method at the final addition stage of Column Bypassing Multiplier and Modified Booth Encoder Multiplier for low power applications. The proposed MBEM encoder is designed with only one XOR with two inputs and two outputs. Between two outputs, one is taken at before of an inverter, the function is XNOR. The second is taken at after the inverter for XOR function.

N° de réf. du vendeur 9783659953422

Détails bibliographiques

• Titre: Low Power and High Speed Parallel Multipliers for DSP Applications : Performance Evaluation of Low Power and High Speed Bypassing and Booth Multipliers for Digital Signal Processing
• Éditeur: LAP LAMBERT Academic Publishing
• Date de parution: 2016
• Langue: anglais
• ISBN à 10 chiffres: 3659953423
• ISBN à 13 chiffres: 9783659953422
• Reliure: Taschenbuch
• État de l'article: Neu
• Dimensions: 220 L x 150 H x 12 P (en millimètres) 220 millimètres de largeur par 150 millimètres de hauteur par 12 millimètres de profondeur
• Poids: 298 grammes

A propos de ce titre

Synopsis

The remarkable increase in transistor densities in modern VLSI systems has direct to a surge in power and energy dissipation to levels not seen before. This tendency will continue to produce as more transistors are packed into the same area. Therefore, power and energy-aware design flows are becoming trendy in both ends of the design space, high-performance and portable applications. In this study, the power and energy reduction techniques at the architecture, circuit, and device levels are presented. With the intention of diminishing power, we proposed a novel method for Conventional Array Multiplier. In the proposed design, final adder RCA is removed and the generated carry bits from the partial products are fed to the input of a full adder cell whose one of the input is zero. We applied final adder RCA removal method at the final addition stage of Column Bypassing Multiplier and Modified Booth Encoder Multiplier for low power applications. The proposed MBEM encoder is designed with only one XOR with two inputs and two outputs. Between two outputs, one is taken at before of an inverter, the function is XNOR. The second is taken at after the inverter for XOR function.