Low-Power Noc for High-Performance Soc Design

Kangmin Lee

ISBN 10: 1420051725 / ISBN 13: 9781420051728

Edité par CRC Press Mär 2008, 2008

A propos de cet article

Neuware - Chip Design and Implementation from a Practical ViewpointFocusing on chip implementation, Low-Power NoC for High-Performance SoC Design provides practical knowledge and real examples of how to use network on chip (NoC) in the design of system on chip (SoC). It discusses many architectural and theoretical studies on NoCs, including design methodology, topology exploration, quality-of-service guarantee, low-power design, and implementation trials. The Steps to Implement NoC The book covers the full spectrum of the subject, from theory to actual chip design using NoC. Employing the Unified Modeling Language (UML) throughout, it presents complicated concepts, such as models of computation and communication-computation partitioning, in a manner accessible to laypeople. The authors provide guidelines on how to simplify complex networking theory to design a working chip. In addition, they explore the novel NoC techniques and implementations of the Basic On-Chip Network (BONE) project. Examples of real-time decisions, circuit-level design, systems, and chips give the material a real-world context. Low-Power NoC and Its Application to SoC Design Emphasizing the application of NoC to SoC design, this book shows how to build the complicated interconnections on SoC while keeping a low power consumption.

N° de réf. du vendeur 9781420051728

Détails bibliographiques

• Titre: Low-Power Noc for High-Performance Soc Design
• Éditeur: CRC Press Mär 2008
• Date de parution: 2008
• Langue: anglais
• ISBN à 10 chiffres: 1420051725
• ISBN à 13 chiffres: 9781420051728
• Reliure: Buch
• État de l'article: Neu
• Dimensions: 240 L x 155 H x 19 P (en millimètres) 240 millimètres de largeur par 155 millimètres de hauteur par 19 millimètres de profondeur
• Poids: 535 grammes

A propos de ce titre

Synopsis

Chip Design and Implementation from a Practical Viewpoint

Focusing on chip implementation, Low-Power NoC for High-Performance SoC Design provides practical knowledge and real examples of how to use network on chip (NoC) in the design of system on chip (SoC). It discusses many architectural and theoretical studies on NoCs, including design methodology, topology exploration, quality-of-service guarantee, low-power design, and implementation trials.

The Steps to Implement NoC

The book covers the full spectrum of the subject, from theory to actual chip design using NoC. Employing the Unified Modeling Language (UML) throughout, it presents complicated concepts, such as models of computation and communication–computation partitioning, in a manner accessible to laypeople. The authors provide guidelines on how to simplify complex networking theory to design a working chip. In addition, they explore the novel NoC techniques and implementations of the Basic On-Chip Network (BONE) project. Examples of real-time decisions, circuit-level design, systems, and chips give the material a real-world context.

Low-Power NoC and Its Application to SoC Design

Emphasizing the application of NoC to SoC design, this book shows how to build the complicated interconnections on SoC while keeping a low power consumption.

À propos de l'auteur

Hoi-Jun Yoo, Kangmin Lee, Jun Kyong Kim