Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL

Ciletti, Michael D.

ISBN 10: 0139773983 / ISBN 13: 9780139773983

Edité par Pearson, 1999

A propos de cet article

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N° de réf. du vendeur 28Z46_80_0139773983

Détails bibliographiques

• Titre: Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL
• Éditeur: Pearson
• Date de parution: 1999
• Langue: anglais
• ISBN à 10 chiffres: 0139773983
• ISBN à 13 chiffres: 9780139773983
• Reliure: Paperback
• État de l'article: new

A propos de ce titre

Synopsis

• Designed for advanced undergraduate and graduate computer science, computer engineering and electrical engineering courses in digital design and hardware description languages, this textbook presents an integrated treatment of the Verilog hardware description language (HDL) and its use in VLSI, circuit modeling/design, synthesis, and rapid prototyping.
• This product is a selection from the Xilinx Design Series.

À propos de la quatrième de couverture

Designed for advanced undergraduate and graduate computer science, computer engineering and electrical engineering courses in digital design and hardware description languages, this textbook presents an integrated treatment of the Verilog hardware description language (HDL) and its use in VLSI, circuit modeling/design, synthesis, and rapid prototyping.

This product is a selection from the Xilinx Design Series.

Back Cover

Designers facing the challenge of the next millennium must have the tools to exploit the rapidly advancing technology of cell-based and other ASIC device technologies, such as Field-Programmable Gate Arrays (FPGAs). It is clear that the leverage offered to designers by hardware description languages will continue to shape design methodologies at all levels of integration, from Programmable Logic Devices (PLDs) to Application-Specific Integrated Circuits (ASICs) and full-custom parts. This impact will continue to develop as more designers embrace HDL-based tools. Many of today's design flows for ASICs and FPGAs typically rely on synthesis tools that optimize and map Verilog HDL descriptions into physical netlists, thereby reducing the design cycle while increasing the opportunity for design exploration. The growing acceptance of this design paradigm suggests that an increasing number of designers will need to know how to be productive users of Verilog in the future. This book presents an integrated treatment of the Verilog hardware description language (HDL) and its use in Very Large Scale Integrated (VLSI) circuit modeling/design, synthesis, and rapid prototyping.

Included with the text are the SILOS® III Verilog development and simulation environment of Simucad, Inc., and the Xilinx® Foundation Express Student Edition, Version 2.1, software tools. This suite of PC-based software tools combined with the text makes an invaluable learning environment for digital designers.