Network -On-Chip (NOC) Design Using FPGA Technology: With implement optimizations in the FSMs and decoding logic

Jain, Manish (Author)

ISBN 10: 613891936X / ISBN 13: 9786138919360

Edité par Scholars' Press, 2019

A propos de cet article

76 pages. 6.00x0.18x9.00 inches. In Stock.

N° de réf. du vendeur __613891936X

Détails bibliographiques

• Titre: Network -On-Chip (NOC) Design Using FPGA Technology: With implement optimizations in the FSMs and decoding logic
• Éditeur: Scholars' Press
• Date de parution: 2019
• Langue: anglais
• ISBN à 10 chiffres: 613891936X
• ISBN à 13 chiffres: 9786138919360
• Reliure: Paperback
• État de l'article: Brand New
• Poids: 0,13 kilogramme

A propos de ce titre

Synopsis

NoC is new paradigm for System-on-chip (SoC) design. NoC based system accommodate multiple asynchronous clocking that many of today's complex SoC design use.The NoC solutions bring a Networking method on-chip communication and claim roughly a performance increases over conventional bus system. As a systematic approach, Network-on-Chip (NoC) called also Network-on-Silicon, proposes networks as a scalable, reusable and global communication architecture to overcome the pains of future System-on-Chip.The idea of NoC is derived from large-scale computer networks and distributed computing. However, the routing techniques for NoC have some unique design considerations besides low latency and high throughput. Due to tight constraints on memory and computing resources, the routing techniques for NoC should be reasonably simple. Several switch architectures have been developed for NoC employing XY output selection and wormhole routing.NoC is a layered approach for on-chip communication design proposed in literature to cope with issues of current SoC architectures. A scalable communication infrastructure that better supports the trend of SoC integration consists of an on-chip packet-swit.