Vendeur
ThriftBooks-Reno, Reno, NV, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Vendeur AbeBooks depuis 25 mai 2012
May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 0.35. N° de réf. du vendeur G0792377885I4N00
Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labour costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
Titre : Principles of Verifiable Rtl Design: A ...
Éditeur : Kluwer Academic Publishers
Date d'édition : 2000
Reliure : Hardcover
Etat : Very Good
Etat de la jaquette : No Jacket
Vendeur : Munster & Company LLC, ABAA/ILAB, Corvallis, OR, Etats-Unis
Etat : Good. Kluwer Academic Publishers, 2000. Cover very barely rubbed, top spine end/bottom corners bumped; fore-edge very barely soiled; binding tight; cover, edges, and interior intact and very clean; a nice copy. hardcover. Good. N° de réf. du vendeur 594941
Quantité disponible : 1 disponible(s)
Vendeur : Better World Books, Mishawaka, IN, Etats-Unis
Etat : As New. 1st Edition. Used book that is in almost brand-new condition. N° de réf. du vendeur 50877156-6
Quantité disponible : 1 disponible(s)
Vendeur : Better World Books: West, Reno, NV, Etats-Unis
Etat : Very Good. 1st Edition. Used book that is in excellent condition. May show signs of wear or have minor defects. N° de réf. du vendeur 5102596-6
Quantité disponible : 2 disponible(s)
Vendeur : ThriftBooks-Atlanta, AUSTELL, GA, Etats-Unis
Hardcover. Etat : Very Good. No Jacket. May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 0.35. N° de réf. du vendeur G0792377885I4N00
Quantité disponible : 1 disponible(s)
Vendeur : ThriftBooks-Phoenix, Phoenix, AZ, Etats-Unis
Hardcover. Etat : Very Good. No Jacket. May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 0.35. N° de réf. du vendeur G0792377885I4N00
Quantité disponible : 1 disponible(s)
Vendeur : Thomas F. Pesce', Anaheim, CA, Etats-Unis
Hard Cover. Etat : Very Good. Purple covers and spine with bold clear, lettering. Pages are clean, tight and bright. The prior owner's initials are printed on the top pages' edges. N° de réf. du vendeur 6022313
Quantité disponible : 1 disponible(s)
Vendeur : BIBLIOPE by Calvello Books, Oakland, CA, Etats-Unis
Hardcover. Etat : near fine(+). Purple octavo; xvii, 253 p, b&w illus; 24 cm. Contents: Register Transfer Level --; What is It? --; Verifiable RTL --; Applying Design Discipline --; The Verification Process --; Specification Design Decomposition --; High-Level Design Requirements --; Block-Level Specification and Design --; RTL Implementation --; Synthesis and Physical Design --; Functional Test Strategies --; Deterministic or Directed Test --; Random Test --; Transaction Analyzer Verification --; Chip Initialization Verification --; Synthesizable Testbench --; Transformation Test Strategies --; Coverage, Events and Assertions --; Coverage --; Ad-hoc Metrics --; Programming Code Metrics --; State Machine and Arc Coverage Metrics --; User Defined Metrics --; Fault Coverage Metrics --; Regression Analysis and Test Suite Optimization --; Event Monitors and Assertion Checkers --; Events --; Assertions --; Assertion Monitor Library Details --; Event Monitor and Assertion Checker Methodology --; Linting Strategy --; Implementation Considerations --; Event Monitor Database and Analysis --; RTL Methodology Basics --; Simple RTL Verifiable Subset --; Linting --; Linting in a design project --; Lint description --; Project Oriented --; Linting Message Examples --; Object-Based Hardware Design --; OBHD and Simulation --; OBHD and Formal Verification --; OBHD and Physical Design --; OBHD Synthesis --; OBHD Scan Chain Hookup --; A Text Macro Implementation --; RTL Logic Simulation --; Simulation History --; First Steps --; X, Z and Other States --; Function and Timing --; Gate to RTL Migration --; Acceleration and Emulation --; Language Standardization. Integrated circuits -- Very large scale integration -- Computer-aided design. Faint rubbed fold to spine head & foot & folds, barely rubbed corners, else near fine(+). First edition (presumed; no earlier dates stated). N° de réf. du vendeur 23856
Quantité disponible : 1 disponible(s)
Vendeur : The Book Bin, Salem, OR, Etats-Unis
Hardcover. Etat : Very Good. Signed by authors Lionel Bening and Harry Foster at the first page. Covers very good with only minor shelf-wear. Spine square. Binding sound. No jacket, as issued. Prior owner's name penned to top of textblock. Pages else clean, interior bright and unmarked. Signed. N° de réf. du vendeur BBS-2020342
Quantité disponible : 1 disponible(s)
Vendeur : The Book Spot, Sioux Falls, MN, Etats-Unis
Hardcover. N° de réf. du vendeur Abebooks205643
Quantité disponible : 1 disponible(s)
Vendeur : Anybook.com, Lincoln, Royaume-Uni
Etat : Good. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,650grams, ISBN:9780792377887. N° de réf. du vendeur 5834192
Quantité disponible : 1 disponible(s)