Diode Switch based 17-level inverter with lesser power electronic elements.- 28GHz 5G Receiver Design using 65nm CMOS and Performance Analysis through Simulation.- Study and implementation of ladder logic conversion to VHDL for Field programmable gate array (FPGA) based Programmable Logic Controllers (PLC).- Automated Monitoring and Regulation of User Friendly Greenhouse using Arduino.- An Involution Function Based Symmetric Stream Cipher.- Multi-Objective Optimization of Block Size based on CPU Power & Network Bandwidth for Blockchain Applications
Dr. Vijay Nath was born in Gorakhpur (U.P.) India in 1976. He received his bachelor's degree in Physics and master's degree in Electronics from DDU Gorakhpur University, India, in 1998 and 2001. He also received PGDCN (GM) from MMMUT Gorakhpur in 1999. He received his Ph.D. degree in VLSI Design & Technology from Dr. RML Avadh University Faizabad in association with CEERI, Pilani, in 2008. From 2000 to 2001, he served as project trainee in IC Design Group, CEERI, Pilani, under the guidance of Dr. K.S.Yadav (Senior Scientist). From 2002 to 2006, he severed as Faculty in the Department of Electronics, DDU University Gorakhpur. Presently, he is an Associate Professor in the Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi (JH), India, and joined this institute in 2006. He has academic and administrative responsibilities such as Professor In-charge of Embedded System Design Lab, Advisor of NAPS (News & Publication Society), member of BIT Mesra Brand Management, Faculty Advisor IEI Student Chapter (ECE) BIT Mesra and Honorary Secretary of IETE Ranchi Centre. He is the recipient of Viveka Nanda Techno Fiesta Award-2002, Young Scientist Award-2004, CCSN Best Paper Award-2013, First Prize in IEI Technical Contest-2013 and Cadence Design Contest-2014, 2016. His research interests include microelectronics, nanoelectronics, analog, digital, mixed CMOS VLSI circuits, low-power VLSI circuits, ultra-low-power CMOS temperature sensor, ADC, DAC, PTAT, CMOS bandgap voltage reference, ASICs, embedded systems designs, smart cardiac pacemaker, smart grids, Internet of things and early stage cancer detection. He has to his credit around 150 publications in reputed Scopus & SCI journals, Scopus books and conferences. He has successfully completed two R&D projects funded by DST New Delhi jointly with DRDL Hyderabad and MHRD New Delhi, and the third project is in ongoing stage funded by RESPOND SAC ISRO Ahmadabad, Government of India. He has developed VLSI Design course under Developing Suitable Pedagogical Methods for Various Classes, Intellectual Calibres & Research in E-learning sponsored by the Ministry of Human Resource Development Government of India. Now the complete course is available in IIT Kharagpur official website and opens for all IITs, NITs, BITs and technical universities of India & abroad. He is the resource person of 16 Winter & Summer School on Digital VLSI Design. He is the program coordinator and resource person of one day seminar/workshop on Electronic System Design & Manufacturing (ESDM), East Zone of India funded by MHRD New Delhi under the aegis of IETE New Delhi. He has conducted 15 ESDM workshops in IITs NITs, BITs and other university/college of India in FY2015-16. He is the Editor of four books Proceeding of International Conference on Nanoelectronics Circuits & Communication Systems (NCCS-2015) & NCCS-2017 and Proceeding of International Conference on Microelectronics Computing & Communication Systems (MCCS-2015) & MCCS-2018 published in Scopus book series: Lecture Notes of Electrical Engineering, Springer. He is a member of several professional societies and academic bodies including IETE, ISTE, ISVE and IEEE.
Prof. J.K. Mandal received his M.Sc. in Physics from Jadavpur University in 1986 and M.Tech. in Computer Science from the University of Calcutta and was awarded a Ph.D. in Computer Science and Engineering by Jadavpur University in 2000. Currently, he is a Professor of Computer Science and Engineering and was Dean of the Faculty of Engineering, Technology and Management, Kalyani University, West Bengal, for two consecutive terms. He started his career as a Lecturer at NERIST, Arunachal Pradesh, in September 1988 and has 30 years' teaching and research experience. His areas of research include coding theory, data and network security, remote sensing and GIS-based applications, data compression, error correction, visual cryptography, steganography, security in MANET, wireless networks and unify computing. He has been a life member of the Computer Society of India since 1992, CRSI since 2009, ACM since 2012, IEEE since 2013 and a Fellow of IETE since 2012. He has chaired more than 60 sessions at various international conferences and delivered more than 60 experts/invited lectures during the last 5 years. He has acted as a program chair of several international conferences and edited more than 30 proceedings volumes. He is a Reviewer for various international journals and conferences and has published over 360 articles and 6 books. He is one of the Editors for the Springer AISC and CCIS Series. He has published more than 450 articles out of which 160 papers are published in the international journal. He has authored 7 books. 23 scholars were awarded Ph.D. degree under his supervision.
