Routing Congestion in VLSI Circuits: Estimation and Optimization

Saxena, Prashant (Author)/ Shelar, Rupesh S. (Author)/ Sapatnekar, Sachin (Author)

ISBN 10: 1441940138 / ISBN 13: 9781441940131

Edité par Springer, 2007

A propos de cet article

250 pages. 9.20x6.10x0.70 inches. In Stock.

N° de réf. du vendeur x-1441940138

Détails bibliographiques

• Titre: Routing Congestion in VLSI Circuits: Estimation and Optimization
• Éditeur: Springer
• Date de parution: 2007
• Langue: anglais
• ISBN à 10 chiffres: 1441940138
• ISBN à 13 chiffres: 9781441940131
• Reliure: Paperback
• État de l'article: Brand New
• Poids: 0,41 kilogramme

A propos de ce titre

Synopsis

This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Présentation de l'éditeur

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.