Routing Congestion in VLSI Circuits

Prashant Saxena

ISBN 10: 1441940138 / ISBN 13: 9781441940131

Edité par Springer US, Springer New York Nov 2010, 2010

A propos de cet article

This item is printed on demand - Print on Demand Titel. Neuware -With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid ¿tra c jams¿; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ow congestion-aware. The book explores this tradeo that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ow.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 264 pp. Englisch.

N° de réf. du vendeur 9781441940131

Détails bibliographiques

• Titre: Routing Congestion in VLSI Circuits
• Éditeur: Springer US, Springer New York Nov 2010
• Date de parution: 2010
• Langue: anglais
• ISBN à 10 chiffres: 1441940138
• ISBN à 13 chiffres: 9781441940131
• Reliure: Taschenbuch
• État de l'article: Neu
• Dimensions: 235 L x 155 H x 15 P (en millimètres) 235 millimètres de largeur par 155 millimètres de hauteur par 15 millimètres de profondeur
• Poids: 406 grammes

A propos de ce titre

Synopsis

This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Présentation de l'éditeur

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.