Source Level Debugging of Verilog Designs | Automated Source Level Debugging of HDL Designs

Naveed Riaz

ISBN 10: 3639262875 / ISBN 13: 9783639262872

Edité par VDM Verlag Dr. Müller, 2010

A propos de cet article

Source Level Debugging of Verilog Designs | Automated Source Level Debugging of HDL Designs | Naveed Riaz | Taschenbuch | Deutsch | VDM Verlag Dr. Müller | EAN 9783639262872 | Verantwortliche Person für die EU: VDM Verlag Dr. Müller, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.

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Détails bibliographiques

• Titre: Source Level Debugging of Verilog Designs | Automated Source Level Debugging of HDL Designs
• Éditeur: VDM Verlag Dr. Müller
• Date de parution: 2010
• Langue: allemand
• ISBN à 10 chiffres: 3639262875
• ISBN à 13 chiffres: 9783639262872
• Reliure: Taschenbuch
• État de l'article: Neu

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Synopsis

Debugging is a very crucial part of hardware design cycle. Once a design is completed, all the possible faults need to be located and corrected. Although the complexity of hardware design is ever increasing, debugging is still mostly performed manually. Today, debugging has become a very painstaking and time consuming task. Model-based diagnosis provides a solid foundation for automated debugging and fault localization but sometimes the quality of the results is questionable as too many diagnosis candidates are reported. The work presented in this book shows how to apply model-based diagnosis to debugging of synthesizable Verilog designs. Moreover, Two extensions of the model based debugging theory to improve the debugging process in terms of reduction in the number of diagnosis candidates reported, are proposed.