Switch-Level Timing Simulation of MOS VLSI Circuits

Rao Vasant B. Trick Timothy Overhauser David V.

ISBN 10: 0898383021 / ISBN 13: 9780898383027

Edité par Springer, 1988

A propos de cet article

PRINT ON DEMAND pp. 224.

N° de réf. du vendeur 183109841

Détails bibliographiques

• Titre: Switch-Level Timing Simulation of MOS VLSI Circuits
• Éditeur: Springer
• Date de parution: 1988
• Langue: anglais
• ISBN à 10 chiffres: 0898383021
• ISBN à 13 chiffres: 9780898383027
• Reliure: Couverture rigide
• État de l'article: New

A propos de ce titre

Synopsis

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com- puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.