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Covers verification strategies and methodologies for SOC verification from system level verification to the design sign-off. This book contains topics including: Introduction to the SOC design and verification aspects; System level verification in brief; Block level verification; Analog/mixed signal simulation; and Simulation. Num Pages: 372 pages, 22 black & white illustrations, biography. BIC Classification: T; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 243 x 164 x 29. Weight in Grams: 796. . 2000. Hardback. . . . . Books ship from the US and Ireland. N° de réf. du vendeur V9780792372790
System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
Titre : System-on-a-Chip Verification
Éditeur : Kluwer Academic Publishers
Date d'édition : 2000
Reliure : Couverture rigide
Etat : New