SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling

Flake, Peter,Davidmann, Simon,Sutherland, Stuart

ISBN 10: 1402075308 / ISBN 13: 9781402075308

Edité par Springer, 2003

A propos de cet article

Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! N° de réf. du vendeur S_432942481

Détails bibliographiques

Titre : SystemVerilog For Design: A Guide to Using ...

Éditeur : Springer

Date d'édition : 2003

Reliure : Hardcover

Etat : Good

A propos de ce titre

Synopsis :

SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, "SystemVerilog for Design", addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, "SystemVerilog for Verification", covers the second aspect of SystemVerilog.