SystemVerilog for Design Second Edition : A Guide to Using SystemVerilog for Hardware Design and Modeling

Stuart Sutherland

ISBN 10: 1441941258 / ISBN 13: 9781441941251

Edité par Springer US, Springer US, 2010

A propos de cet article

Druck auf Anfrage Neuware - Printed after ordering - SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.In addition, the second edition features a new chapter that explanis the SystemVerilog 'packages', a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools. N° de réf. du vendeur 9781441941251

Détails bibliographiques

Titre : SystemVerilog for Design Second Edition : A ...

Éditeur : Springer US, Springer US

Date d'édition : 2010

Reliure : Taschenbuch

Etat : Neu

Edition : 2ème Édition

A propos de ce titre

Synopsis :

In its updated second edition, this book has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes adopted between the first edition of the book and the finalization of the new standard. The book accurately reflects the syntax and semantic changes to the SystemVerilog language, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter that explains the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

Présentation de l'éditeur:

In its updated second edition, this book has been rewritten chapter-by-chapter to accurately reflect the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information