SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Spear, Chris

ISBN 10: 0387765298 / ISBN 13: 9780387765297

Edité par Springer (edition 2nd), 2008

The item might be beaten up but readable. May contain markings or highlighting, as well as stains, bent corners, or any other major defect, but the text is not obscured in any way. N° de réf. du vendeur 0387765298-7-1

Synopsis :

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

Détails bibliographiques

Titre : SystemVerilog for Verification: A Guide to ...
Éditeur : Springer (edition 2nd)
Date d'édition : 2008
Reliure : Hardcover
Etat : Fair
Edition : 2nd.