SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Chris Spear

ISBN 10: 0387270361 / ISBN 13: 9780387270364

Edité par Springer, 2007

May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less 1.6. N° de réf. du vendeur G0387270361I4N00

Synopsis :

"SystemVerilog for Verification" provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

Détails bibliographiques

Titre : SystemVerilog for Verification: A Guide to ...
Éditeur : Springer
Date d'édition : 2007
Reliure : Hardcover
Etat : Very Good
Etat de la jaquette : No Jacket