Transactions on High-Performance Embedded Architectures and Compilers V

Cristina Silvano

ISBN 10: 3662588331 / ISBN 13: 9783662588338

Edité par Springer Berlin Heidelberg, 2019

A propos de cet article

Druck auf Anfrage Neuware - Printed after ordering - Transactions on HiPEAC aims at the timely dissemination of researchcontributions in computer architecture and compilation methods forhigh-performance embedded computer systems. Recognizing the convergenceof embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks aswell as systems with broad application bases. The scope of the journaltherefore covers all aspects of computerarchitecture, code generationand compiler optimization methods of interest to researchers andpractitioners designing future embedded systems.This 5th issue contains extended versions of papers by the best paper award candidates of IC-SAMOS 2009 and the SAMOS 2009 Workshop, colocated events of the 9th International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS 2009, held in Samos, Greece, in 2009. The 7 papers included in this volume were carefully reviewed and selected. The papers coverresearch on embedded processor hardware/software design and integration and present challenging research trends. N° de réf. du vendeur 9783662588338

Détails bibliographiques

Titre : Transactions on High-Performance Embedded ...

Éditeur : Springer Berlin Heidelberg

Date d'édition : 2019

Reliure : Taschenbuch

Etat : Neu

A propos de ce titre

Synopsis :

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.-Programmable and Scalable Architecture for Graphics Processing Units.- Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs.- A Hardware-Accelerated Estimation-Based Power Profiling Unit. - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management.- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors.- Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability.- A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.