Ultra-low Power Processor Design Using Subthreshold Design Techniques

Zhai, Bo/ Blaauw, David/ Sylvester, Dennis

ISBN 10: 3836497867 ISBN 13: 9783836497862
Edité par Vdm Verlag Dr Mueller E K, 2008
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184 pages. 9.00x6.00x0.50 inches. In Stock. N° de réf. du vendeur 3836497867

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Power consumption is becoming worse with every technology generation. While there has been much research in recent years proposing design methods addressing this issue, one of the most efficient approaches is to reduce supply voltage. In our research, we found the optimal voltage (Vmin) for energy efficiency in CMOS technology. We analyzed the different factors affecting Vmin and find that Vmin usually lies in subthreshold voltage regime. To verify the high energy efficiency of subthreshold operation, we designed and fabricated two subthreshold processors in 0.13um technology, specifically, the Subliminal 1 and Subliminal 2 processors. Measurements confirm 2.60pJ per instruction efficiency for the Subliminal 1. Also, we designed and fabricated the first sub-200mV compact 6-T SRAM in a commercial 0.13um CMOS technology. Silicon measurements show that all 24 dies measured were fully functional and a typical die operates from 1.2V to 193mV. Then to address the lost performance from voltage scaling, we proposed a novel micro-architecture and found that having multiple cores sharing one faster local L1 provides the best energy efficiency.

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Titre : Ultra-low Power Processor Design Using ...
Éditeur : Vdm Verlag Dr Mueller E K
Date d'édition : 2008
Reliure : Paperback
Etat : Brand New

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Bo Zhai|David Blaauw|Dennis Sylvester
Edité par VDM Verlag Dr. Müller, 2010
ISBN 10 : 3836497867 ISBN 13 : 9783836497862
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Kartoniert / Broschiert. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Zhai BoBo Zhai received his B.S. degree in microelectronics from Peking University, China, in 2002, his M.S. and Ph.D. in Electrical Engineering from the University of Michigan, in 2004 and 2007. His research focuses on low power V. N° de réf. du vendeur 5390027

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Bo Zhai (u. a.)
Edité par VDM Verlag Dr. Müller, 2010
ISBN 10 : 3836497867 ISBN 13 : 9783836497862
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Taschenbuch. Etat : Neu. Ultra-Low Power Processor Design Using Subthreshold Design Techniques | The Solution to Battery Life with Voltage Scaling | Bo Zhai (u. a.) | Taschenbuch | 184 S. | Englisch | 2010 | VDM Verlag Dr. Müller | EAN 9783836497862 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. N° de réf. du vendeur 106169244

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Bo Zhai
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ISBN 10 : 3836497867 ISBN 13 : 9783836497862
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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Power consumption is becoming worse with every technology generation. While there has been much research in recent years proposing design methods addressing this issue, one of the most efficient approaches is to reduce supply voltage. In our research, we found the optimal voltage (Vmin) for energy efficiency in CMOS technology. We analyzed the different factors affecting Vmin and find that Vmin usually lies in subthreshold voltage regime. To verify the high energy efficiency of subthreshold operation, we designed and fabricated two subthreshold processors in 0.13um technology, specifically, the Subliminal 1 and Subliminal 2 processors. Measurements confirm 2.60pJ per instruction efficiency for the Subliminal 1. Also, we designed and fabricated the first sub-200mV compact 6-T SRAM in a commercial 0.13um CMOS technology. Silicon measurements show that all 24 dies measured were fully functional and a typical die operates from 1.2V to 193mV. Then to address the lost performance from voltage scaling, we proposed a novel micro-architecture and found that having multiple cores sharing one faster local L1 provides the best energy efficiency. N° de réf. du vendeur 9783836497862

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Power consumption is becoming worse with every technology generation. While there has been much research in recent years proposing design methods addressing this issue, one of the most efficient approaches is to reduce supply voltage. In our research, we found the optimal voltage (Vmin) for energy efficiency in CMOS technology. We analyzed the different factors affecting Vmin and find that Vmin usually lies in subthreshold voltage regime. To verify the high energy efficiency of subthreshold operation, we designed and fabricated two subthreshold processors in 0.13um technology, specifically, the Subliminal 1 and Subliminal 2 processors. Measurements confirm 2.60pJ per instruction efficiency for the Subliminal 1. Also, we designed and fabricated the first sub-200mV compact 6-T SRAM in a commercial 0.13um CMOS technology. Silicon measurements show that all 24 dies measured were fully functional and a typical die operates from 1.2V to 193mV. Then to address the lost performance from voltage scaling, we proposed a novel micro-architecture and found that having multiple cores sharing one faster local L1 provides the best energy efficiency. 184 pp. Englisch. N° de réf. du vendeur 9783836497862

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Bo Zhai
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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Power consumption is becoming worse with every technology generation. While there has been much research in recent years proposing design methods addressing this issue, one of the most efficient approaches is to reduce supply voltage. In our research, we found the optimal voltage (Vmin) for energy efficiency in CMOS technology. We analyzed the different factors affecting Vmin and find that Vmin usually lies in subthreshold voltage regime. To verify the high energy efficiency of subthreshold operation, we designed and fabricated two subthreshold processors in 0.13um technology, specifically, the Subliminal 1 and Subliminal 2 processors. Measurements confirm 2.60pJ per instruction efficiency for the Subliminal 1. Also, we designed and fabricated the first sub-200mV compact 6-T SRAM in a commercial 0.13um CMOS technology. Silicon measurements show that all 24 dies measured were fully functional and a typical die operates from 1.2V to 193mV. Then to address the lost performance from voltage scaling, we proposed a novel micro-architecture and found that having multiple cores sharing one faster local L1 provides the best energy efficiency.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 184 pp. Englisch. N° de réf. du vendeur 9783836497862

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