Verification Techniques for System-Level Design

Masahiro Fujita

ISBN 10: 0124054617 / ISBN 13: 9780124054615

Edité par Morgan Kaufmann, 2014

A propos de cet article

250 pages. 9.25x7.50x0.57 inches. In Stock.

N° de réf. du vendeur zk0124054617

Détails bibliographiques

• Titre: Verification Techniques for System-Level Design
• Éditeur: Morgan Kaufmann
• Date de parution: 2014
• Langue: anglais
• ISBN à 10 chiffres: 0124054617
• ISBN à 13 chiffres: 9780124054615
• Reliure: Paperback
• État de l'article: Brand New

A propos de ce titre

Synopsis

This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal' and 'semiformal' verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional' verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.