Verilog and SystemVerilog Gotchas

Don Mills

ISBN 10: 1441944028 / ISBN 13: 9781441944023

Edité par Springer US, Springer US Nov 2010, 2010

A propos de cet article

Neuware -In programming, ¿Gotchä is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly.This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors.This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 236 pp. Englisch.

N° de réf. du vendeur 9781441944023

Détails bibliographiques

• Titre: Verilog and SystemVerilog Gotchas
• Éditeur: Springer US, Springer US Nov 2010
• Date de parution: 2010
• Langue: anglais
• ISBN à 10 chiffres: 1441944028
• ISBN à 13 chiffres: 9781441944023
• Reliure: Taschenbuch
• État de l'article: Neu

A propos de ce titre

Synopsis

This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them. This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.

Présentation de l'éditeur

This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages.