Constraint-Based Verification (Paperback)

Jun Yuan

ISBN 10: 1441938524 / ISBN 13: 9781441938527

Edité par Springer-Verlag New York Inc., New York, NY, 2010

A propos de cet article

Paperback. Constraint-Based Verification covers an emerging field in functional verification of electronic designs, referred to as the "constraint-based verification." The topics are developed in the context of a wide range of dynamic and static verification approaches including simulation, emulation, and formal methods. The goal is to show how constraints, or assertions, can be used towards automating the generation of testbenches, resulting in a seamless verification flow. Topics such as verification coverage, and connection with assertion based verification, are also covered.The book targets verification engineers as well as researchers. It covers both methodological and technical issues. Particular stress is given to the latest advances in functional verification.The research community has witnessed recent growth of interests in constraint-based functional verification. Various techniques have been developed. They are relatively new, but have reached a level of maturity so that they are appearing in commercial tools such as Vera and System Verilog. Constraint-Based Verification covers an emerging field in functional verification of electronic designs, referred to as the "constraint-based verification." Topics such as verification coverage, and connection with assertion based verification, are also covered.The book targets verification engineers as well as researchers. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

N° de réf. du vendeur 9781441938527

Détails bibliographiques

• Titre: Constraint-Based Verification (Paperback)
• Éditeur: Springer-Verlag New York Inc., New York, NY
• Date de parution: 2010
• Langue: anglais
• ISBN à 10 chiffres: 1441938524
• ISBN à 13 chiffres: 9781441938527
• Reliure: Paperback
• Édition: Edition originale
• État de l'article: new

A propos de ce titre

Synopsis

As the complexity and miniaturization of electronic hardware advances, more time and money is actually now spent on testing and verification than in the preliminary design stage. This practical-oriented guidebook covers both the fundamentals and the techniques of constraint-based testbench automation. The book compares and contrasts constraint-based verification with traditional testbench approaches: test generation (a key concept), simulation monitoring, and coverage. Related aspects of verification languages such as e/vera/PSL/OVL/SVA are also covered. On the technical side, state-of-the art algorithms of test generation, performance optimization, and randomization are explained.