Digital Design and Modeling with VHDL and Synthesis (Systems)

Chang, K. C.

ISBN 10: 0818677163 / ISBN 13: 9780818677168

Edité par Wiley-IEEE Computer Society Pr, 1997

A propos de cet article

Ships in a BOX from Central Missouri! May not include working access code. Will not include dust jacket. Has used sticker(s) and some writing or highlighting. UPS shipping for most packages, (Priority Mail for AK/HI/APO/PO Boxes).

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Détails bibliographiques

• Titre: Digital Design and Modeling with VHDL and Synthesis (Systems)
• Éditeur: Wiley-IEEE Computer Society Pr
• Date de parution: 1997
• Langue: anglais
• ISBN à 10 chiffres: 0818677163
• ISBN à 13 chiffres: 9780818677168
• Reliure: hardcover
• Édition: 1st Edition.
• État de l'article: Good

A propos de ce titre

Synopsis

Digital Systems Design with VHDL and Synthesis presents an integrated approach to digital design principles, processes, and implementations to help the reader design much more complex systems within a shorter design cycle. This is accomplished by introducing digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together.

The author focuses on the ultimate product of the design cycle: the implementation of a digital design. VHDL coding, synthesis methodologies and verification techniques are presented as tools to support the final design implementation. Readers will understand how to apply and adapt techniques for VHDL coding, verification, and synthesis to various situations.

Digital Systems Design with VHDL and Synthesis is a result of K.C. Chang's practical experience in both design and as an instructor. Many of the design techniques and considerations illustrated throughout the chapters are examples of viable designs. His teaching experience leads to a step-by-step presentation that addresses common mistakes and hard-to-understand concepts in a way that eases learning.

Unique features of the book include the following:

• VHDL code explained line by line to capture the logic behind the design concepts
• VHDL is verified using VHDL test benches and simulation tools
• Simulation waveforms are shown and explained to verify design correctness
• VHDL code is synthesized and commands and strategies are discussed. Synthesized schematics and results are analyzed for area and timing
• Variations on the design techniques and common mistakes are addressed; Demonstrated standard cell, gate array, and FPGA three design processes
• Each with a complete design case study
• Test bench, post-layout verification, and test vector generation processes.

Practical design concepts and examples are presented with VHDL code, simulation waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships.

À propos de l?auteur

Kwang-chih Chang, commonly known as K.C. Chang, was a Chinese-American archaeologist and sinologist. He was the John E. Hudson Professor of archaeology at Harvard University, Vice-President of the Academia Sinica, and a curator at the Peabody Museum of Archaeology and Ethnology.