Low-Power Design of Nanometer FPGAs: Architecture and Eda

Anis, Mohab;Hassan, Hassan

ISBN 10: 0123744385 / ISBN 13: 9780123744388

Edité par Morgan Kaufmann/Elsevier, Saint Louis, Missouri, U.S.A., 2010

A propos de cet article

This is a New and U&nread copy of the first edition.

N° de réf. du vendeur 032089

Détails bibliographiques

• Titre: Low-Power Design of Nanometer FPGAs: Architecture and Eda
• Éditeur: Morgan Kaufmann/Elsevier, Saint Louis, Missouri, U.S.A.
• Date de parution: 2010
• Langue: anglais
• ISBN à 10 chiffres: 0123744385
• ISBN à 13 chiffres: 9780123744388
• Reliure: Hardcover
• Édition: 1st Edition
• État de l'article: As New
• État de la jaquette: None Issued

A propos de ce titre

Synopsis

Field Programmable Gate Arrays (FPGAs) have become very popular as embedded components on computing platforms. An FPGA is a viable, reprogrammable design approach that provides a fast time-to-market alternative to Application Specific Integrated Circuits (ASICs). Since FPGA implementations can be customized to fit for any application, their versatility leads to performance gains, and enables reuse of expensive silicon. Although high performance can be achieved in FPGAs, their high levels of power consumption pose a critical design challenge.

This book will be an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques will be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.

* Design perspective on low-power FPGAs...low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesign;
* Low-leakage design in FPGAs...comprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipation;
* FPGA power estimation techniques...provides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques.

À propos des auteurs

Hassan Hassan is currently a staff engineer in the timing and power group at Actel Corporation. He has authored/coauthored more than 20 papers in international journals and conferences. His research interests include integrated circuit design and design automation for deep submicron VLSI systems. He is also a member of the program committee for several IEEE conferences. Dr. Hassan received his Ph.D. in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2008.

Mohab Anis is a tenured Associate Professor at the Department of Electrical and Computer Engineering, University of Waterloo. During 2009, he was with the Electronics Engineering Department at the American University in Cairo. Dr. Anis received his Ph.D. in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2003. Dr. Anis is an Associate Editor of the IEEE Transactions on Circuits and Systems - II, Microelectronics Journal, Journal of Circuits, Systems and Computers, ASP Journal of Low Power Electronics, and VLSI Design. He was awarded the 2009 Early Research Award, the 2004 Douglas R. Colton Medal for Research Excellence in recognition of excellence in research leading to new understanding and novel developments in Microsystems in Canada and the 2002 International Low-Power Design Contest.