Principles of Verifiable Rtl Design:; a functional coding style supporting verification processes in Verilog

Bening, Lionel; Foster, Harry

ISBN 10: 0792377885 / ISBN 13: 9780792377887

Edité par Kluwer Academic Publishers, Norwell, Mass, 2000

A propos de cet article

Purple octavo; xvii, 253 p, b&w illus; 24 cm. Contents: Register Transfer Level --; What is It? --; Verifiable RTL --; Applying Design Discipline --; The Verification Process --; Specification Design Decomposition --; High-Level Design Requirements --; Block-Level Specification and Design --; RTL Implementation --; Synthesis and Physical Design --; Functional Test Strategies --; Deterministic or Directed Test --; Random Test --; Transaction Analyzer Verification --; Chip Initialization Verification --; Synthesizable Testbench --; Transformation Test Strategies --; Coverage, Events and Assertions --; Coverage --; Ad-hoc Metrics --; Programming Code Metrics --; State Machine and Arc Coverage Metrics --; User Defined Metrics --; Fault Coverage Metrics --; Regression Analysis and Test Suite Optimization --; Event Monitors and Assertion Checkers --; Events --; Assertions --; Assertion Monitor Library Details --; Event Monitor and Assertion Checker Methodology --; Linting Strategy --; Implementation Considerations --; Event Monitor Database and Analysis --; RTL Methodology Basics --; Simple RTL Verifiable Subset --; Linting --; Linting in a design project --; Lint description --; Project Oriented --; Linting Message Examples --; Object-Based Hardware Design --; OBHD and Simulation --; OBHD and Formal Verification --; OBHD and Physical Design --; OBHD Synthesis --; OBHD Scan Chain Hookup --; A Text Macro Implementation --; RTL Logic Simulation --; Simulation History --; First Steps --; X, Z and Other States --; Function and Timing --; Gate to RTL Migration --; Acceleration and Emulation --; Language Standardization. Integrated circuits -- Very large scale integration -- Computer-aided design. Faint rubbed fold to spine head & foot & folds, barely rubbed corners, else near fine(+). First edition (presumed; no earlier dates stated).

N° de réf. du vendeur 23856

Détails bibliographiques

• Titre: Principles of Verifiable Rtl Design:; a functional coding style supporting verification processes in Verilog
• Éditeur: Kluwer Academic Publishers, Norwell, Mass
• Date de parution: 2000
• Langue: anglais
• ISBN à 10 chiffres: 0792377885
• ISBN à 13 chiffres: 9780792377887
• Reliure: Hardcover
• Édition: Edition originale
• État de l'article: near fine(+)
• Catalogues du vendeur:
  • Science, Technology & Computers

A propos de ce titre

Synopsis

Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labour costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.