White hardcover with black lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. N� de r�f. du vendeur 249534

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D�tails bibliographiques

Titre : Switch-Level Timing Simulation of MOS VLSI ...

�diteur : Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.

Date d'�dition : 1989

Reliure : hardcover

Etat : Very Good

Etat de la jaquette : No Dust Jacket

Edition : First Edition.

Type de livre : Used

A propos de ce titre

Synopsis :

Book by Rao Vasant B Overhauser David V Trick Timothy Hajj

Les informations fournies dans la section � A propos du livre � peuvent faire r�f�rence � une autre �dition de ce titre.

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Articles li�s � Switch-Level Timing Simulation of MOS VLSI Circuits...

Switch-Level Timing Simulation of MOS VLSI Circuits (The Kluwer International Series in Engineering and Computer Science; 66. VLSI, Computer Architecture and Digital Signal Processing)

Rao, Vasant; Overhauser, David; Trick, Timothy; Hajj, Ibrahim

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