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Ajouter au panierHardcover. Etat : Good. No Jacket. Former library book; Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 1.13.
EUR 6,17
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Ajouter au panierEtat : Good. 1987th Edition. Former library book; may include library markings. Used book that is in clean, average condition without any missing pages.
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EUR 17,68
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Ajouter au panierhardcover. Etat : Very Good. Pages are crisp and clean, no marking. Cover is verygood. Binding is tight/good.
Edité par Springer-Verlag New York Inc., New York, NY, 2010
ISBN 10 : 1441952012 ISBN 13 : 9781441952011
Langue: anglais
Vendeur : Grand Eagle Retail, Bensenville, IL, Etats-Unis
Edition originale
EUR 161,08
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Ajouter au panierPaperback. Etat : new. Paperback. In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
EUR 157,56
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Ajouter au panierEtat : New.
Edité par Kluwer Academic Publishers, Dordrecht, 1987
ISBN 10 : 0898382440 ISBN 13 : 9780898382440
Langue: anglais
Vendeur : Grand Eagle Retail, Bensenville, IL, Etats-Unis
EUR 161,41
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierHardcover. Etat : new. Hardcover. In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
EUR 157,90
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Ajouter au panierEtat : New.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 159,03
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Ajouter au panierEtat : New. In.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 159,03
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Ajouter au panierEtat : New. In.
EUR 209,46
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Ajouter au panierEtat : New. pp. 224.
Edité par Kluwer Academic Publishers, 1987
ISBN 10 : 0898382440 ISBN 13 : 9780898382440
Langue: anglais
Vendeur : Kennys Bookshop and Art Galleries Ltd., Galway, GY, Irlande
EUR 199,58
Autre deviseQuantité disponible : 15 disponible(s)
Ajouter au panierEtat : New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 209 pages, biography. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 14. Weight in Grams: 498. . 1987. Hardback. . . . .
Edité par Springer US, Springer US Sep 1987, 1987
ISBN 10 : 0898382440 ISBN 13 : 9780898382440
Langue: anglais
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
EUR 160,49
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Ajouter au panierBuch. Etat : Neu. Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 226 pp. Englisch.
EUR 167,14
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Ajouter au panierTaschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.
Edité par Springer US, Springer US, 1987
ISBN 10 : 0898382440 ISBN 13 : 9780898382440
Langue: anglais
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
EUR 168,73
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierBuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.
Edité par Kluwer Academic Publishers, 1987
ISBN 10 : 0898382440 ISBN 13 : 9780898382440
Langue: anglais
Vendeur : Kennys Bookstore, Olney, MD, Etats-Unis
EUR 250,47
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Ajouter au panierEtat : New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 209 pages, biography. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 14. Weight in Grams: 498. . 1987. Hardback. . . . . Books ship from the US and Ireland.
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
EUR 233,58
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Ajouter au panierHardcover. Etat : Very Good. Very Good. book.
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
EUR 245,43
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Ajouter au panierPaperback. Etat : Like New. Like New. book.
Edité par Springer-Verlag New York Inc., New York, NY, 2010
ISBN 10 : 1441952012 ISBN 13 : 9781441952011
Langue: anglais
Vendeur : AussieBookSeller, Truganina, VIC, Australie
Edition originale
EUR 278,03
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierPaperback. Etat : new. Paperback. In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.
Edité par Kluwer Academic Publishers, Dordrecht, 1987
ISBN 10 : 0898382440 ISBN 13 : 9780898382440
Langue: anglais
Vendeur : AussieBookSeller, Truganina, VIC, Australie
EUR 294,74
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Ajouter au panierHardcover. Etat : new. Hardcover. In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.
Edité par Springer, Chapman And Hall/CRC Dez 2010, 2010
ISBN 10 : 1441952012 ISBN 13 : 9781441952011
Langue: anglais
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
EUR 160,49
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Ajouter au panierTaschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. 224 pp. Englisch.
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
EUR 160,49
Autre deviseQuantité disponible : 2 disponible(s)
Ajouter au panierBuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. 226 pp. Englisch.
Vendeur : preigu, Osnabrück, Allemagne
EUR 141,05
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Ajouter au panierBuch. Etat : Neu. Yield Simulation for Integrated Circuits | D. M. Walker | Buch | xii | Englisch | 1987 | Springer US | EAN 9780898382440 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand.
Edité par Springer US, Springer US Dez 2010, 2010
ISBN 10 : 1441952012 ISBN 13 : 9781441952011
Langue: anglais
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
EUR 160,49
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierTaschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 224 pp. Englisch.
Vendeur : Majestic Books, Hounslow, Royaume-Uni
EUR 221,48
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Ajouter au panierEtat : New. Print on Demand pp. 224 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
Vendeur : Biblios, Frankfurt am main, HESSE, Allemagne
EUR 224,81
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Ajouter au panierEtat : New. PRINT ON DEMAND pp. 224.