Articles liés à Bias Temperature Instability for Devices and Circuits
Synopsis
Part I.- Bias Temperature Instability Characterization Methods.- Application of on-chip device heating for BTI investigations.- Statistical Characterization of BTI Induced High-k Dielectric Traps in Nanoscale Transistors.- The time dependent defect spectroscopy.- Analysis of Oxide Traps in Nanoscale MOSFETs using Random Telegraph Noise.- BTI Induced Statistical Variations.- Statistical Distribution of Defect Parameters.- Atomic Scale Defects Associated with the Negative Bias Temperature Instability.- Charge Properties of Paramagnetic Defects in Semiconductor/Oxide Structures.- Oxide Defects.- Understanding Negative-Bias Temperature Instability from Dynamic Stress Experiments.- Part II.- Atomistic Modeling of Defects Implicated in the Bias Temperature Instability.- Statistical Study of Bias Temperature Instabilities by means of 3D 'Atomistic' Simulation.- A Comprehensive Modeling Framework for DC and AC NBTI.- On the Microscopic Limit of the RD Model.- Advanced Modeling of Oxide Defects.- The Capture/Emission Time Map Approach to the Bias Temperature Instability.- FEOL and BEOL Process Dependence of NBTI.- Negative Bias Temperature Instability in Thick Gate Oxides for Power MOS Transistors.- NBTI and PBTI in High-k Metal Gate.- PBTI in High-k Oxides.- Characterization of Individual Traps in High-k Oxides.- NBTI in (Si)Ge channel devices.- Characteristics of NBTI in Multi-Gate FETs for Highly-Scaled CMOS Technology.- Bias-Temperature Instabilities in Silicon Carbide MOS Devices.- Part IV.- On-Chip Silicon Odometers for Circuit Aging Characterization.- Multi-level Reliability Simulation for IC Design.- Charge trapping in MOSFETS: BTI and RTN Modeling for Circuits.- Simulation of BTI related time-dependent variability in CMOS circuits.
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