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VEasy: a Tool Suite for Teaching Functional Verification: Teaching the principles of Functional Verification in an intuitive way - Couverture souple

Nascimento Pagliarini, Samuel; Lima Kastensmidt, Fernanda

 
9783659143328: VEasy: a Tool Suite for Teaching Functional Verification: Teaching the principles of Functional Verification in an intuitive way
Couverture souple
ISBN 10 : 3659143324 ISBN 13 : 9783659143328
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

This book describes a tool suite, VEasy, which was developed specifically for aiding the process of teaching Functional Verification. VEasy contains four main modules that perform linting, simulation, coverage collection/analysis and testcase generation, which are considered key challenges to achieve verification success. Each of those modules is commented in details throughout the chapters. All the modules are integrated and built on top of a Graphical User Interface. This framework enables the testcase automation methodology which is based on layers, where one is capable of creating complex test scenarios using drag-and-drop operations. Whenever possible examples are given using simple Verilog designs. The capabilities of the tool and its performance are also compared with some commercial and academic functional verification tools.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

This book describes a tool suite, VEasy, which was developed specifically for aiding the process of teaching Functional Verification. VEasy contains four main modules that perform linting, simulation, coverage collection/analysis and testcase generation, which are considered key challenges to achieve verification success. Each of those modules is commented in details throughout the chapters. All the modules are integrated and built on top of a Graphical User Interface. This framework enables the testcase automation methodology which is based on layers, where one is capable of creating complex test scenarios using drag-and-drop operations. Whenever possible examples are given using simple Verilog designs. The capabilities of the tool and its performance are also compared with some commercial and academic functional verification tools.

Biographie de l'auteur

Samuel is currently a researcher at Télécom ParisTech, Paris, France. He received the titles of Computer Eng. and Master in Microelectronics in 2008 and 2011, respectively, from Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil. His main research interests are circuit design/verification, fault tolerance and single-event effects.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3659143324
ISBN 13 
9783659143328
Reliure
Broché
Nombre de pages
120
Coordonnées du fabricant
non disponible
Personne responsable
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