Low Power Latch Designs in Subthreshold Region: Designs for Portable applications - Couverture souple

Sharma, Krishna Gopal; Choudhary, Abhilasha; Sharma, Tripti

 
9783659160615: Low Power Latch Designs in Subthreshold Region: Designs for Portable applications
Couverture souple
ISBN 10 : 365916061X ISBN 13 : 9783659160615
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.

Biographie de l'auteur

Received B.E. degree in E&C from MMM Engineering College, Gorakhpur, and M.Tech. in VLSI Design from MITS, Sikar. He is currently pursuing Ph.D. from SGVU, Jaipur in Low Power VLSI Device design. He has published research papers in reputed journals and conferences. He is also editorial board member and reviewer of well reputed journals.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
365916061X
ISBN 13 
9783659160615
Reliure
Broché
Nombre de pages
80
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
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