CMOS Low Power Analysis: Scaling effect & Power Delay Analysis - Couverture souple

SHARMA, VIJAY

 
9783844382778: CMOS Low Power Analysis: Scaling effect & Power Delay Analysis

Synopsis

In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.

Biographie de l'auteur

I have received M.Tech. in VLSI Design from NIT Hamirpur (H.P.) and B.Tech. in Electronics & Communication Engineering from UPTU Lucknow (U.P.). Now i am doing lot of research work on low power VLSI field.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.