Dual Core RISC Processor with configurable hardware using VERILOG

Kumar, Nishant; Aggrawal, Ekta

ISBN 10: 3659417882 / ISBN 13: 9783659417887

Edité par LAP LAMBERT Academic Publishing, 2015

In. N° de réf. du vendeur ria9783659417887_new

Synopsis :

This book proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements to achieve high sequential performance and high parallel performance. Processor provides two execution modes. Mode1 is multiprogramming mode for execution of streams of instruction of lower data width, i.e., each core can perform 16-bit operations individually. Performance is improved in this mode due to the parallel execution of instructions in both the cores at the cost of area. In mode2, both the processing cores are coupled and behave like single, high data width processing unit, i.e., can perform 32-bit operation. Additional core-to-core communication is needed to realise this mode. The mode can switch dynamically; therefore, this processor can provide multifunction with single design. Design and verification of processor has been done successfully using Verilog on Xilinx 14.1 platform. The processor is verified in both simulation and synthesis with the help of test programs.

Détails bibliographiques

Titre : Dual Core RISC Processor with configurable ...
Éditeur : LAP LAMBERT Academic Publishing
Date d'édition : 2015
Reliure : Couverture souple
Etat : New