Fault Tolerant & Testable Sequential Reversible Circuit Design

Vishal Pareek

ISBN 10: 3659671681 / ISBN 13: 9783659671685

Edité par LAP LAMBERT Academic Publishing Jan 2015, 2015

A propos de cet article

This item is printed on demand - it takes 3-4 days longer - Neuware -Fast growing computing demands the power consumption and chip size issues are posing challenges for logic design with conventional technologies because of the above reliability in conventional technologies is also becoming important. Reversible computing is emerging as an alternative that offers high computation speed, high packaging density and low heat dissipation. This book expands on many of the most popular reversible computing topics such as sequential reversible building block, parity preservation and fault tolerant characteristics of sequential circuits for addressing the reliability issues. In this book, we have reported a Pareek gate suitable for low cost flip-flops design and then design methodology to develop flip-flops are incorporated. Finally, these circuits have been converted into fault tolerant circuits by preserving their parity and designs of offline as well as online testable circuits have been proposed. In addition, the text book presents the statistical results of proposed designs over quantum cost as well as other optimization parameters with existing circuits in literature and a significant improvement is achieved in almost all the parameters. 76 pp. Englisch.

N° de réf. du vendeur 9783659671685

Détails bibliographiques

• Titre: Fault Tolerant & Testable Sequential Reversible Circuit Design
• Éditeur: LAP LAMBERT Academic Publishing Jan 2015
• Date de parution: 2015
• Langue: anglais
• ISBN à 10 chiffres: 3659671681
• ISBN à 13 chiffres: 9783659671685
• Reliure: Taschenbuch
• État de l'article: Neu