Low Power Flash ADC

Murra Subba Reddy

ISBN 10: 3845440848 / ISBN 13: 9783845440842

Edité par LAP LAMBERT Academic Publishing Aug 2011, 2011

A propos de cet article

Neuware -In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.Books on Demand GmbH, Überseering 33, 22297 Hamburg 80 pp. Englisch.

N° de réf. du vendeur 9783845440842

Détails bibliographiques

• Titre: Low Power Flash ADC
• Éditeur: LAP LAMBERT Academic Publishing Aug 2011
• Date de parution: 2011
• Langue: anglais
• ISBN à 10 chiffres: 3845440848
• ISBN à 13 chiffres: 9783845440842
• Reliure: Taschenbuch
• État de l'article: Neu

A propos de ce titre

Synopsis

In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.