Springer us copernicus jun 2004 (4 résultats)
- Couverture rigide
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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagnebuchversandmimpf2000
Contacter le vendeurVendeur avec une évaluation de 5 étoilesEtat: Neuf
EUR 106,99
EUR 60,00 expéditionExpédition depuis Allemagne vers Etats-UnisQuantité disponible : 1 disponible(s)
Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in… a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 140 pp. Englisch.
- Couverture rigide
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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagnebuchversandmimpf2000
Contacter le vendeurVendeur avec une évaluation de 5 étoilesEtat: Neuf
EUR 106,99
EUR 60,00 expéditionExpédition depuis Allemagne vers Etats-UnisQuantité disponible : 1 disponible(s)
Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditi…onally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios.This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including:Spatial pruning - reducing aggressors to those in physical proximityElectrical pruning - reducing aggressors by electrical strengthTemporal pruning - reducing aggressors using timing windowsFunctional pruning - reducing aggressors by Boolean functional analysis.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 132 pp. Englisch.
- Couverture rigide
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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagnebuchversandmimpf2000
Contacter le vendeurVendeur avec une évaluation de 5 étoilesEtat: Neuf
EUR 160,49
EUR 60,00 expéditionExpédition depuis Allemagne vers Etats-UnisQuantité disponible : 1 disponible(s)
Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Rapid advances in microelectronic integration and the advent of Systems-on-Chip have fueled the need for high-level synthesis, i.e., an automated approach to the synthesis of hardware from behavioral descriptions. SPARK: A Parallelizing Approach t…o the High - Level Synthesis of Digital Circuits presents a novel approach to the high-level synthesis of digital circuits -- that of parallelizing high-level synthesis (PHLS). This approach uses aggressive code parallelizing and code motion techniques to discover circuit optimization opportunities beyond what is possible with traditional high-level synthesis. This PHLS approach addresses the problems of the poor quality of synthesis results and the lack of controllability over the transformations applied during the high-level synthesis of system descriptions with complex control flows, that is, with nested conditionals and loops. Also described are speculative code motion techniques and dynamic compiler transformations that optimize the circuit quality in terms of cycle time, circuit size and interconnect costs. We describe the SPARK parallelizing high-level synthesis framework in which we have implemented these techniques and demonstrate the utility of SPARK's PHLS approach using designs derived from multimedia and image processing applications. We also present a case study of an instruction length decoder derived from the Intel Pentium-class of microprocessors. This case study serves as an example of a typical microprocessor functional block with complex control flow and demonstrates how our techniques are useful for such designs. SPARK: A Parallelizing Approach to the High - Level Synthesis of Digital Circuits is targeted mainly to embedded system designers and researchers. This includes people working on design and design automation. The book is useful for researchers and design automation engineers who wish to understand how the main problems hindering the adoption of high-level synthesis among designers.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 264 pp. Englisch.
- Couverture rigide
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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagnebuchversandmimpf2000
Contacter le vendeurVendeur avec une évaluation de 5 étoilesEtat: Neuf
EUR 160,49
EUR 60,00 expéditionExpédition depuis Allemagne vers Etats-UnisQuantité disponible : 1 disponible(s)
Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -One of the grand challenges in the nano-scopic computing era is guarantees of robustness. Robust computing system design is confronted with quantum physical, probabilistic, and even biological phenomena, and guaranteeing high reliability is much m…ore difficult than ever before. Scaling devices down to the level of single electron operation will bring forth new challenges due to probabilistic effects and uncertainty in guaranteeing 'zero-one' based computing. Minuscule devices imply billions of devices on a single chip, which may help mitigate the challenge of uncertainty by replication and redundancy. However, such device densities will create a design and validation nightmare with the shear scale.The questions that confront computer engineers regarding the current status of nanocomputing material and the reliability of systems built from such miniscule devices, are difficult to articulate and answer. We have found a lack of resources in the confines of a single volume that at least partially attempts to answer these questions.We believe that this volume contains a large amount of research material as well as new ideas that will be very useful for some one starting research in the arena of nanocomputing, not at the device level, but the problems one would face at system level design and validation when nanoscopic physicality will be present at the device level.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 376 pp. Englisch.
