Memory management unit (14 résultats)

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware component responsible for handling accesses to memory requested by the CPU. Its functions include translation of virtual addresses to physical addresses (i.e., virtual memory management), memory protection, cache control, bus arbitration, and, in simpler computer architectures (especially 8-bit systems), bank switching. 76 pp. Englisch.…

Taschenbuch. Etat : Neu. IOMMU | Computing, Memory management unit, Direct memory access, Main memory, Computer bus, Virtual address, Physical address | Frederic P. Miller (u. a.) | Taschenbuch | Englisch | 2026 | OmniScriptum | EAN 9786131843105 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand. …

Taschenbuch. Etat : Neu. Memory Management Unit | Computer hardware, Computer memory, Central processing unit, Virtual address, Physical address, Virtual memory, Memory protection | Frederic P. Miller (u. a.) | Taschenbuch | Englisch | 2026 | OmniScriptum | EAN 9786130793708 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.…

Taschenbuch. Etat : Neu. Atari MMU | Memory Management Unit, Atari 8-Bit, Atari FREDDIE | Lambert M. Surhone (u. a.) | Taschenbuch | Englisch | 2026 | OmniScriptum | EAN 9786134613286 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand. …

Taschenbuch. Etat : Neu. Bus Error | Computing, Computer data storage, CPU, Software bug, Computer hardware, Source code, Memory address, Address bus, Exception handling, Segmentation fault, Memory management unit | Frederic P. Miller (u. a.) | Taschenbuch | Englisch | 2026 | OmniScriptum | EAN 9786130757885 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. The Atari MMU is a custom MMU chip for the Atari 8-bit computers. It enables access to the hardware registers on ANTIC, GTIA, POKEY and 6520 PIA. The later XL/XE MMU (C061618) also selects OS ROM, Atari BASIC ROM, self-test ROM and LEDs in the 1200XL. The user cannot directly manipulate the Atari MMU, but selects the various ROMS and memory via the memory-mapped hardware register known as PORTB (5401710 or D30116). Atari changed PORTB from an input port on the 400/800 machines to an output port on the XL/XE machines, leaving two joystick ports instead of four on the XL/XE machines.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articlesavailable from Wikipedia or other free sources online. Extended PageTable (EPT) is an Intel second generation x86 virtualization technologyfor the memory management unit (MMU). When this feature is active, theordinary IA-32 page tables (referenced by control register CR3)translate from linear addresses to guest-physical addresses. A separateset of page tables (the EPT tables) translate from guest-physicaladdresses to the host-physical addresses that are used to access memory.As a result, guest software can be allowed to modify its own IA-32 pagetables and directly handle page faults. This allows a virtual machinemanager (VMM) to avoid the VM exits associated with page-tablevirtualization, which are a major source of virtualization overheadwithout EPT.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articlesavailable from Wikipedia or other free sources online. INTEGRITY is areal-time operating system (RTOS) produced and marketed by Green HillsSoftware. It is royalty-free, POSIX-certified, and intended for use inembedded systems needing reliability, availability, and fault tolerance.It is built atop the velOSity microkernel and is intended mainly formodern 32- or 64- bit embedded system designs that support an MMU.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articlesavailable from Wikipedia or other free sources online. Texture memory isa type of digital storage that makes texture data readily available tovideo rendering processors (also known as GPUs), typically 3D graphicshardware. It is most often (but not always) implemented as specializedRAM (TRAM) that is designed for rapid reading and writing, enabling thegraphics hardware increased performance in rendering 3D imagery. Largeramounts of texture memory allow for more detailed scenes.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articlesavailable from Wikipedia or other free sources online. In computing, aninput/output memory management unit (IOMMU) is a memory management unit(MMU) that connects a DMA-capable I/O bus to the main memory. Like atraditional MMU, which translates CPU-visible virtual addresses tophysical addresses, the IOMMU takes care of mapping device-visiblevirtual addresses (also called device addresses or I/O addresses in thiscontext) to physical addresses. Some units also provide memoryprotection from misbehaving devices.…

Taschenbuch. Etat : Neu. CPU Cache | Central processing unit, Translation lookaside buffer, Cache coloring, Cache coherence, List of computer term etymologies, High-performance computing, Virtual memory, Memory management unit | Frederic P. Miller (u. a.) | Taschenbuch | Englisch | 2026 | OmniScriptum | EAN 9786130040581 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer instruction set architecture, including both required and optional components, as described by the military standard document MIL-STD-1750A. In addition to the core ISA, the definition defines optional instructions, such as a FPU and MMU. Importantly, the standard does not define the implementation details of a 1750A processor. The 1750A supports 216 16-bit words of memory for the core standard. The standard defines an optional memory management unit that allows 220 16-bit words of memory using 512 page mapping registers, defining separate instruction and data spaces, and keyed memory access control.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering.