Articles liés à Hierarchical Modeling for Vlsi Circuit Testing
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- ÉditeurSpringer
- Date d'édition1989
- ISBN 10 079239058X
- ISBN 13 9780792390589
- ReliureRelié
- Langueanglais
- Nombre de pages160
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Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Edité par
Springer, 1989
ISBN 10 : 079239058X
ISBN 13 : 9780792390589
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Etat : very_good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in very good condition! The cover and any other included accessories are also in very good condition showing some minor use. The spine is straight, there are no rips tears or creases on the cover or the pages. N° de réf. du vendeur GWSVV.079239058X.VG
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Hierarchical Modeling for VLSI Circuit Testing (The Kluwer International Series in Engineering and Computer Science)
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Kluwer, 1989
ISBN 10 : 079239058X
ISBN 13 : 9780792390589
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Hardcover. 1990. 160 Seiten Ehem. Bibliotheksexemplar mit üblichen Merkmalen wie Signatur und Stempel. Moderate Lager- und Gebrauchsspuren. Text bis auf selten mögliche Anstreichungen sauber. Insgesamt guter Zustand. Sprache: englisch. Ex library book with stamps and signature. Slight signs of use. Good condition. Language: english. 9780792390589 Sprache: Englisch Gewicht in Gramm: 939. N° de réf. du vendeur 1106144
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Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
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Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
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Hierarchical Modelling for Very Large Scale Integration Circuit Testing (Kluwer International Series in Engineering & Computer Science, Vlsi, Computer Architecture & Digit)
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Kluwer Academic Publishers, 1989
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ISBN 13 : 9780792390589
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Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
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Hierarchical Modeling for VLSI Circuit Testing
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Hierarchical Modeling for VLSI Circuit Testing
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Gebunden. Etat : New. Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated . N° de réf. du vendeur 458443287
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Hierarchical Modeling for VLSI Circuit Testing
Edité par
Springer Us Dez 1989, 1989
ISBN 10 : 079239058X
ISBN 13 : 9780792390589
Neuf
Couverture rigide
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
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Buch. Etat : Neu. Neuware - Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. N° de réf. du vendeur 9780792390589
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