Articles liés à Hierarchical Modeling for Vlsi Circuit Testing
Synopsis
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob- lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Acheter neuf
Afficher cet article
EUR 57,08
EUR 10,41 expédition depuis Royaume-Uni vers France
Destinations, frais et délaisAutres éditions populaires du même titre
Résultats de recherche pour Hierarchical Modeling for Vlsi Circuit Testing
Image fournie par le vendeur
Hierarchical Modeling for VLSI Circuit Testing (The Kluwer International Series in Engineering and Computer Science)
Edité par
Kluwer, 1989
ISBN 10 : 079239058X
ISBN 13 : 9780792390589
Ancien ou d'occasion
Couverture rigide
Vendeur : Antiquariat Bookfarm, Löbnitz, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Hardcover. 1990. 160 Seiten Ehem. Bibliotheksexemplar mit üblichen Merkmalen wie Signatur und Stempel. Moderate Lager- und Gebrauchsspuren. Text bis auf selten mögliche Anstreichungen sauber. Insgesamt guter Zustand. Sprache: englisch. Ex library book with stamps and signature. Slight signs of use. Good condition. Language: english. 9780792390589 Sprache: Englisch Gewicht in Gramm: 939. N° de réf. du vendeur 1106144
Quantité disponible : 1 disponible(s)
Image d'archives
Hierarchical Modelling for Very Large Scale Integration Circuit Testing (Kluwer International Series in Engineering & Computer Science, Vlsi, Computer Architecture & Digit)
Edité par
Kluwer Academic Publishers, 1989
ISBN 10 : 079239058X
ISBN 13 : 9780792390589
Neuf
Couverture rigide
Vendeur : New Book Sale, London, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Hardcover. Etat : New. Usually Dispatched within 1-2 Business Days , Buy with confidence , excellent customer service. N° de réf. du vendeur 079239058X--56
Quantité disponible : 5 disponible(s)
Image d'archives
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Vendeur : BOOKWEST, Phoenix, AZ, Etats-Unis
Évaluation du vendeur 3 sur 5 étoiles
Hardcover. Etat : New. US SELLER SHIPS FAST FROM USA. N° de réf. du vendeur DOM-136B2-079239058X-HC-2P1-Wht
Quantité disponible : 1 disponible(s)
Image d'archives
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9780792390589_new
Quantité disponible : Plus de 20 disponibles
Image d'archives
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Vendeur : Best Price, Torrance, CA, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. SUPER FAST SHIPPING. N° de réf. du vendeur 9780792390589
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
Hierarchical Modeling for VLSI Circuit Testing
Vendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Gebunden. Etat : New. Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated . N° de réf. du vendeur 458443287
Quantité disponible : Plus de 20 disponibles
Image d'archives
Hierarchical Modeling for VLSI Circuit Testing
impression à la demandeVendeur : THE SAINT BOOKSTORE, Southport, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Hardback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 970. N° de réf. du vendeur C9780792390589
Quantité disponible : Plus de 20 disponibles
Image d'archives
Hierarchical Modeling for VLSI Circuit Testing (The Springer International Series in Engineering and Computer Science, 89)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur ABLIING23Feb2416190185611
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Hierarchical Modeling for VLSI Circuit Testing
Edité par
Springer Us Dez 1989, 1989
ISBN 10 : 079239058X
ISBN 13 : 9780792390589
Neuf
Couverture rigide
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Neuware - Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. N° de réf. du vendeur 9780792390589
Quantité disponible : 2 disponible(s)