Isbn: 9786130308063 (3 résultats)

Edité par VDM Verlag Dr. Müller E.K. Dez 2009, 2009
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Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, AllemagneBuchWeltWeit Ludwig Meier e.K.
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EUR 23,00 expéditionExpédition depuis Allemagne vers Etats-UnisQuantité disponible : 2 disponible(s)
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online.The acronym RISC, for reduced instruction set computer, represents a CPU design strategy emphasizing the insight that simplified instructions that 'do less' may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly. Many proposals for a 'precise' definition have been attempted, and the term is being slowly replaced by the more descriptive load-store architecture. Well known RISC families include Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture, SuperH, and SPARC. Englisch.…

Edité par OmniScriptum, 2026
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Vendeur : preigu, Osnabrück, Allemagnepreigu
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Taschenbuch. Etat : Neu. Reduced Instruction Set Computer | Addressing Mode, Complex Instruction Set Computer, Very Long Instruction Word, Minimal Instruction Set Computer | Lambert M. Surhone (u. a.) | Taschenbuch | Englisch | 2026 | OmniScriptum | EAN 9786130308063 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.…

Edité par Omniscriptum
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Vendeur : AHA-BUCH GmbH, Einbeck, AllemagneAHA-BUCH GmbH
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EUR 189,66
EUR 30,50 expéditionExpédition depuis Allemagne vers Etats-UnisQuantité disponible : 1 disponible(s)
Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online.The acronym RISC, for reduced instruction set computer, represents a CPU design strategy emphasizing the insight that simplified instructions that 'do less' may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly. Many proposals for a 'precise' definition have been attempted, and the term is being slowly replaced by the more descriptive load-store architecture. Well known RISC families include Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture, SuperH, and SPARC.…