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Chip design CMOS analog integrated circuit layout design and verification: based on Cadence IC 6.1.7 version 2(Chinese Edition)
CHEN CHENG YING . CHEN LI MING . JIANG JIAN HUA . WANG XING HUA
- Couverture souple
Vendeur : liu xing, Nanjing, JS, Chineliu xing
Contacter le vendeurVendeur avec une évaluation de 5 étoilesEtat: Neuf
EUR 157,41
EUR 15,40 expéditionExpédition depuis Chine vers Etats-UnisQuantité disponible : 3 disponible(s)
paperback. Etat : New. Language:Chinese.Paperback. Pub Date: 2023-12 Pages: 483 Publisher: Machinery Industry Press This book focuses on the field of CMOS analog integrated circuit layout design. Starting from the basic concepts of layout. design methods and EDA tools. it gradually introduces CMOS analog integrated circuit layou…t planning. . layout. design to tape-out; it introduces in detail the current mainstream analog integrated circuit layout design and verification tools - Cadence IC 6.1.7 and Siemens EDA Cal.
