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Ajouter au panierpaperback. Etat : Very Good. Cover and edges may have some wear.
Vendeur : Books From California, Simi Valley, CA, Etats-Unis
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Ajouter au panierpaperback. Etat : Good. Minor shelf wear/ creasing on cover.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 72,22
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Vendeur : California Books, Miami, FL, Etats-Unis
EUR 75,07
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Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
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Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
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Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
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Ajouter au panierEtat : As New. Unread book in perfect condition.
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
EUR 78,85
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EUR 94,43
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Ajouter au panierEtat : New. pp. 510 3rd Edition.
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Ajouter au panierEtat : New. pp. 510 3rd Edition.
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Ajouter au panierEtat : New. pp. 510 720 Illus.
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
EUR 96,64
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EUR 103,85
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Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
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EUR 112,54
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Ajouter au panierEtat : New. Solutions Manual for end of chapter problem being prepared by authors|Completely updated technical material incorporating more fundamentals, latest changes to IEEE specifications since the second edition, and adding end of chapter problems Contain.
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
EUR 113,07
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Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
EUR 66,70
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Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
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Edité par Springer-Verlag New York Inc., US, 2012
ISBN 10 : 1461407141 ISBN 13 : 9781461407140
Langue: anglais
Vendeur : Rarewaves.com UK, London, Royaume-Uni
EUR 150,77
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Ajouter au panierHardback. Etat : New. 3rd ed. 2012. Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students' understanding of the material. Other features of this revision include:New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standardDescriptions of UVM features such as factories, the test registry, and the configuration databaseExpanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulatorsSystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
Edité par Springer-Verlag New York Inc., US, 2012
ISBN 10 : 1461407141 ISBN 13 : 9781461407140
Langue: anglais
Vendeur : Rarewaves.com USA, London, LONDO, Royaume-Uni
EUR 159,14
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierHardback. Etat : New. 3rd ed. 2012. Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students' understanding of the material. Other features of this revision include:New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standardDescriptions of UVM features such as factories, the test registry, and the configuration databaseExpanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulatorsSystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
Vendeur : dsmbooks, Liverpool, Royaume-Uni
EUR 173,27
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Ajouter au panierHardcover. Etat : Like New. Like New. book.
Vendeur : moluna, Greven, Allemagne
EUR 60,06
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Ajouter au panierKartoniert / Broschiert. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Solutions Manual for end of chapter problem being prepared by authors|Completely updated technical material incorporating more fundamentals, latest changes to IEEE specifications since the second edition, and adding end of chapter problems Contain.
Vendeur : Majestic Books, Hounslow, Royaume-Uni
EUR 97,99
Autre deviseQuantité disponible : 4 disponible(s)
Ajouter au panierEtat : New. Print on Demand pp. 510 720 Illus.
Vendeur : Biblios, Frankfurt am main, HESSE, Allemagne
EUR 99,15
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Ajouter au panierEtat : New. PRINT ON DEMAND pp. 510.