Edité par LAP LAMBERT Academic Publishing Mai 2012, 2012
ISBN 10 : 3659128376 ISBN 13 : 9783659128370
Langue: anglais
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
EUR 68
Autre deviseQuantité disponible : 2 disponible(s)
Ajouter au panierTaschenbuch. Etat : Neu. Neuware -Dynamically reconfigurable architectures (DRA) have the potential for achieving high performance at a relatively low cost for a wide range of applications. DRA combine programmable processing units with reconfigurable hardware units. The later is usually based on dynamically reconfigurable Field Programmable Gate Array (FPGA). Designers have used the temporal partitioning approach to divide the application into temporal partitions, which are configured one after the one on target FPGA. The first partition receives input data, performs computations and stores the intermediate data into an on-board memory. The device is then reconfigured for the next partition, which computes results based on intermediate data from the previous partition. A controller interacts with both the reconfigurable hardware and the memory and is used to load new configuration. The temporal partitioning has become an essential issue for several important VLSI applications. Application with several tasks has entailed problem complexities that are unmanageable for existing programmable device.Books on Demand GmbH, Überseering 33, 22297 Hamburg 200 pp. Englisch.
Edité par LAP LAMBERT Academic Publishing, 2012
ISBN 10 : 3659128376 ISBN 13 : 9783659128370
Langue: anglais
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
EUR 137,20
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierPaperback. Etat : Like New. Like New. book.
Edité par LAP LAMBERT Academic Publishing, 2012
ISBN 10 : 3659128376 ISBN 13 : 9783659128370
Langue: anglais
Vendeur : moluna, Greven, Allemagne
EUR 55,21
Autre deviseQuantité disponible : Plus de 20 disponibles
Ajouter au panierEtat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Ouni BouraouiDr Bouraoui Ouni is currently an associate professor at national engineering school of Sousse.Dr. Bouraoui ouni has authored/co-authored over of tens papers in international journals and conferences. He served as a.
Edité par LAP LAMBERT Academic Publishing Mai 2012, 2012
ISBN 10 : 3659128376 ISBN 13 : 9783659128370
Langue: anglais
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
EUR 68
Autre deviseQuantité disponible : 2 disponible(s)
Ajouter au panierTaschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Dynamically reconfigurable architectures (DRA) have the potential for achieving high performance at a relatively low cost for a wide range of applications. DRA combine programmable processing units with reconfigurable hardware units. The later is usually based on dynamically reconfigurable Field Programmable Gate Array (FPGA). Designers have used the temporal partitioning approach to divide the application into temporal partitions, which are configured one after the one on target FPGA. The first partition receives input data, performs computations and stores the intermediate data into an on-board memory. The device is then reconfigured for the next partition, which computes results based on intermediate data from the previous partition. A controller interacts with both the reconfigurable hardware and the memory and is used to load new configuration. The temporal partitioning has become an essential issue for several important VLSI applications. Application with several tasks has entailed problem complexities that are unmanageable for existing programmable device. 200 pp. Englisch.
Edité par LAP LAMBERT Academic Publishing, 2012
ISBN 10 : 3659128376 ISBN 13 : 9783659128370
Langue: anglais
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
EUR 68
Autre deviseQuantité disponible : 1 disponible(s)
Ajouter au panierTaschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Dynamically reconfigurable architectures (DRA) have the potential for achieving high performance at a relatively low cost for a wide range of applications. DRA combine programmable processing units with reconfigurable hardware units. The later is usually based on dynamically reconfigurable Field Programmable Gate Array (FPGA). Designers have used the temporal partitioning approach to divide the application into temporal partitions, which are configured one after the one on target FPGA. The first partition receives input data, performs computations and stores the intermediate data into an on-board memory. The device is then reconfigured for the next partition, which computes results based on intermediate data from the previous partition. A controller interacts with both the reconfigurable hardware and the memory and is used to load new configuration. The temporal partitioning has become an essential issue for several important VLSI applications. Application with several tasks has entailed problem complexities that are unmanageable for existing programmable device.